Dedicated Message Passing Hardware in Multicore

Final Project for 6.175 Constructive Computer Architecture

6.175 is a new subject to learn the fundamental principles of computer architecture via implementation of different versions of pipelined machines with caches, branch predictors and virtual memory. Emphasis on writing and evaluating architectural descriptions that can be both simulated and synthesized into real hardware or run on FPGAs. The use and design of test benches. Weekly labs. Intended for students who want to apply computer science techniques to complex hardware design.

Topics include combinational circuits including adders and multipliers, multi- cycle and pipelined functional units, RISC Instruction Set Architectures (ISA), non-pipelined and multi-cycle processor architectures, 2-to-10 stage in-order pipelined architectures, processors with caches and hierarchical memory systems, TLBs and page faults, I/O interrupts.

For our final project, we implemented a cache-coherent multicore processor with a dedicated message passing bus to bypass cache coherence overhead.

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